1. Field of the Invention
The present invention relates to a digital DLL device, a digital DLL control method and a digital DLL control program capable of providing a delay to an input clock signal so as to equally divide the clock cycle thereof.
2. Description of the Related Art
First of all, as an example of a DLL device, reference will be made to a memory interface used for DDR (Double Data Rate) memories, DDR2 memories, or the like. FIG. 5 is a timing chart showing one example of the timing of a DQS (read data strobe) signal and a DQ (read data) signal in the DDR memory interface. The DQS signal has a clock cycle T. The DQS signal and the DQ signal passed from a DDR memory to an ASIC are aligned with each other in phase at points of changes, and the DQ signal changes at an interval of T/2. Accordingly, it is necessary to provide the DQS signal with a delay of T/4 so as to accurately read data of the DQ signal. Thus, a DLL (Delay Locked Loop) device is used to obtain such a delay as to equally divide the arbitrary clock cycle T in an exact manner.
Next, reference will be made to the configuration of a known DLL device. Here, the DLL device will be described which is able to obtain a delay of a multiple of T/N when assuming that the clock cycle is T and the number by which the clock cycle is equally divided is N. By way of example, a DLL device with the number N being 4 as used with the above-mentioned DDR memory interface will be described.
FIG. 6 is a block diagram showing one example of the configuration of such a known DLL device. This DLL device is provided with four serially connected variable delay sections 1a, 1b, 1c, 1d, a phase comparison section 2 and a delay control section 3. The variable delay sections 1a through 1d output a first output clock signal of a T/4 delay, a second output clock signal of a 2T/4 delay, a third output clock signal of a 3T/4 delay, and a forth output clock signal of a 4T/4 delay, respectively.
Now, the operation of this known DLL device will be explained below. Each of the variable delay sections 1a, 1b, 1c, 1d has an amount of delay of about T/4, and is able to adjust their delay amount in accordance with a control signal from the delay control section 3. The phase comparison section 2 compares the phase of an input clock signal supplied from the outside to the first variable delay section 1a and the phase of the fourth output clock signal output from the last variable delay section 1d, and generates a resultant output to the delay control section 3 as phase difference information. The delay control section 3 determines, based on the phase difference information, a delay amount for each of the variable delay sections 1a, 1b, 1c, 1d, and outputs a control signal representative of the delay amount thus determined to all the variable delay sections 1a, 1b, 1c, 1d, so that the delay amounts of the variable delay sections 1a, 1b, 1c, 1d can be adjusted at a time.
In general, there are two types, analog and digital, in DLL devices. In analog DLL devices, the control signal from the delay control section 3 to the variable delay sections 1a, 1b, 1c, 1d is of an analog quantity, and hence the delay amount of each variable delay section can be adjusted steplessly, but they are vulnerable to noise since a subtle or slight change in the control signal results in a corresponding change in the delay amount. On the other hand, in digital DLL devices, the variable delay sections 1a, 1b, 1c, 1d are each formed of a plurality of unit delay buffers connected in series with each other in a variable manner, so that the total amount of delay is controlled by adjusting the number of stages of unit delay buffers actually or effectively connected with each other. Thus, only discrete amounts of delay can be obtained, but the control signal is of a digital quantity and hence highly resistant to noise. Therefore, digital DLL devices are generally used as DLL devices for memory interfaces.
FIG. 7 is a block diagram showing one example of the configuration of such a known digital DLL device. This digital DLL device is provided with four serially connected variable delay sections 11a, 11b, 11c, 11d, a phase comparison section 12 and a delay control section 13. Each of the variable delay sections 11a, 11b, 11c, 11d is comprised of a plurality of unit delay buffers which are connected in series with one another in such a manner that the number of stages of the unit delay buffers to be electrically or effectively connected with one another is changed by a control signal from the delay control section 13. In the variable delay sections 11a, 11b, 11c, 11d of FIG. 7, those unit delay buffers 15 which are electrically or effectively connected with one another are represented by black square boxes, whereas those unit delay buffers 15a which are not electrically or effectively connected with one another are represented by white square boxes.
The phase comparison section 12 outputs either one of +1, 0 and −1 as phase difference information. Specifically, when the phase of a fourth output clock signal from the last variable delay section 11d advances with respect to the phase of an input clock signal supplied to the first variable delay section 11a, the phase difference information is set to +1; when the phase of the input clock signal and the phase of the fourth output clock signal coincide with each other, the phase difference information is set to 0; and when the output phase of the fourth output clock signal lags with respect to the phase of the input clock signal, the phase difference information is set to−1.
The delay control section 13 determines the number of stages of unit delay buffers in each of the variable delay sections 11a, 11b, 11c, 11d in accordance with the phase difference information from the phase comparison section 12, and outputs it to all the variable delay sections 11a, 11b, 11c, 11d as a control signal. Specifically, when the phase difference information is +1, the number of stages of unit delay buffers for each of all the variable delay sections is increased by 1; when the phase difference information is 0, the number of stages of unit delay buffers for each of all the variable delay sections is not changed; when the phase difference information is −1, the number of stages of unit delay buffers for each of all the variable delay sections is decreased by 1.
Here, note that the amount of delay of each unit delay buffer in an actual digital DLL device is about 30-80 ps (pico seconds) in the case of using a 0.13 μm CMOS process for example, though it varies depending upon the power supply voltage and the operating temperature.
Here, note that the following patent documents are known to be relevant to the present invention.
Japanese patent application laid-open No. H11-86545 (pages 4 through 9 and FIG. 1)
Japanese patent application laid-open No. H11-88153
Japanese patent application laid-open No. 2003-133948
Japanese patent application laid-open No. 2001-285266
In the above-mentioned known digital DLL device, however, in order to divide the clock cycle T into equal parts, one and the same control signal is output from the delay control section 13 to all the variable delay sections 11a, 11b, 11c, 11d. In the case of a digital DLL device obtaining a delay of a multiple of T/4 as in the above-mentioned example, four times the delay amount of each unit delay buffer becomes the unit of adjustment of the entire digital DLL device. Let us consider, as a concrete example, the case in which the amount of delay of each unit delay buffer is 75 ps. In this case, a minimum unit for adjustment of the delay amount of the entire digital DLL device becomes 300 ps.
Further, let us assume that the digital DLL device as employed in this case has a data rate of 400 Mbps, i.e., the entire digital DLL device has a target delay amount in the form of a clock cycle T of 5,000 ps. At this time, the target delay amount T will be obtained if the number of 75 ps unit delay buffers used in the entire digital DLL device is 5,000/75=66.7.
However, in actuality, the number of stages of unit delay buffers for the entire digital DLL device has always to be a natural number which can be devided by 4. Accordingly, when a sufficient time has elapsed after the delay control section 13 starts control operation, the number of stages of unit delay buffers for the entire digital DLL device moves between 64 and 68. At this time, the number of stages of the unit delay buffers used for the first output clock signal moves between 64/4=16 and 68/4=17, so the delay amount of the first output clock signal moves between 75 ps×16=1,200 ps and 75 ps×17=1,275 ps. Comparing the delay amount of the first output clock signal with the target delay amount of T/4=1,250 ps, an error becomes 50 ps at the maximum. In addition, the delay amount of the fourth output clock signal moves between 75 ps×64=4,800 ps and 75 ps×68=5,100 ps, and hence an error becomes 200 ps at the maximum.